Data and memory optimization techniques for embedded systems

Authors:
P. R. Panda;F. Catthoor;N. D. Dutt;K. Danckaert;E. Brockmeyer;C. Kulkarni;A. Vandercappelle;P. G. Kjeldsberg
Affiliations:
Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CA;Inter-University Microelectronics Centre and Katholieke Universiteit Leuven, Kapeldreef 75, Leuven, Belgium;Center for Embedded Computer Systems, University of California at Irvine, Irvine, CA;Inter-University Microelectronics Centre, Kapeldreef 75, Leuven, Belgium;Inter-University Microelectronics Centre, Kapeldreef 75, Leuven, Belgium;Inter-University Microelectronics Centre, Kapeldreef 75, Leuven, Belgium;Inter-University Microelectronics Centre, Kapeldreef 75, Leuven, Belgium;Norwegian University of Science and Technology, Trondheim, Norway
Venue:
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Year:
2001

Citing 118
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Abstract

We present a survey of the state-of-the-art techniques used in performing data and memory-related optimizations in embedded systems. The optimizations are targeted directly or indirectly at the memory subsystem, and impact one or more out of three important cost metrics: area, performance, and power dissipation of the resulting implementation.We first examine architecture-independent optimizations in the form of code transoformations. We next cover a broad spectrum of optimization techniques that address memory architectures at varying levels of granularity, ranging from register files to on-chip memory, data caches, and dynamic memory (DRAM). We end with memory addressing related issues.