Memory-CPU size optimization for embedded system designs

  • Authors:
  • Barry Shackleford;Mitsuhiro Yasuda;Etsuko Okushi;Hisao Koizumi;Hiroyuki Tomiyama;Hiroto Yasuura

  • Affiliations:
  • Hewlett-Packard Laboratories, Palo Alto, CA and Mitsubishi Electric Company, Yokohama 220-81 Japan;Mitsubishi Electric Company, Yokohama 220-81 Japan;Mitsubishi Electric Company, Yokohama 220-81 Japan;Mitsubishi Electric Company, Yokohama 220-81 Japan;Kyushu University, Kasuga-shi 816, Japan;Kyushu University, Kasuga-shi 816, Japan

  • Venue:
  • DAC '97 Proceedings of the 34th annual Design Automation Conference
  • Year:
  • 1997

Quantified Score

Hi-index 0.00

Visualization

Abstract

Entire systems embedded in a chip and consistingof a processor, memory, and system-specific peripheral hardwareare now commonly contained in commodity electronicdevices. Cost minimization of these systems is of paramounteconomic importance to manufactures of these devices. Byemploying a variable configuration processor in conjunctionwith a multi-precision compiler generator there are situationsin which considerable system cost reduction can be obtainedby synthesizing a CPU that is narrower than the largest variablein the application program.