A hardware/software partitioning algorithm for designing pipelined ASIPs with least gate counts

  • Authors:
  • Nguyen Ngoc Bình;Masaharu Imai;Akichika Shiomi;Nobuyuki Hikichi

  • Affiliations:
  • Department of Information and Computer Sciences, Faculty of Engineering Science, Osaka University, Toyonaka-shi, Osaka, 560 Japan and Dept. of Information & Computer Sciences, Toyohashi University ...;Department of Information and Computer Sciences, Faculty of Engineering Science, Osaka University, Toyonaka-shi, Osaka, 560 Japan and Dept. of Information & Computer Sciences, Toyohashi University ...;Department of Computer Science, Faculty of Information, Shizuoka University, Hamamatsu-shi, 432 Japan and Dept. of Information & Computer Sciences, Toyohashi University of Technology, Toyohashi, ...;Dept. of Software Technology, Software Research Associates, Inc., Tokyo, 170 Japan

  • Venue:
  • DAC '96 Proceedings of the 33rd annual Design Automation Conference
  • Year:
  • 1996

Quantified Score

Hi-index 0.00

Visualization

Abstract