A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs

  • Authors:
  • M. Imai;N. Binh;A. Shiomi

  • Affiliations:
  • Dept. of Information & Computer Sciences, Faculty of Engineering Science, Osaka University, 1-3 Machikaneyama-cho, Toyonaka-shi, Osaka, Japan 560;Dept. of Information & Computer Sciences, Faculty of Engineering Science, Osaka University, 1-3 Machikaneyama-cho, Toyonaka-shi, Osaka, Japan 560;Dept. of Computer Science, Faculty of Information, Shizuoka University, 3-5-1 Johoku-cho, Hamamatsu-shi, Shizuoka, Japan 432

  • Venue:
  • EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
  • Year:
  • 1996

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Abstract