Loop acceleration exploration for ASIP architecture

  • Authors:

  • Mame Maria Mbaye;Normand Bélanger;Yvon Savaria;Samuel Pierre

  • Affiliations:

  • Department of Electrical Engineering, Ecole Polytechnique de Montreal, Montreal, QC, Canada;Department of Electrical Engineering, Ecole Polytechnique de Montreal, Montreal, QC, Canada;Department of Electrical Engineering, Ecole Polytechnique de Montreal, Montreal, QC, Canada;Department of Electrical Engineering, Ecole Polytechnique de Montreal, Montreal, QC, Canada

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 2012

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Abstract

Design space exploration is a delicate process whose success lays on the designers' shoulders. It is often based on a trial-and-error approach. Some basic metrics can be used to guide this process. In this paper, we explore accelerating loops from C-based specifications. We built a framework in which a design style, such as software-oriented or application-specific instruction-set processor (ASIP)-oriented design, can be specified. We also propose an exploration process that allows targeting the main aspects that limit acceleration and the actions that can be made to improve it. The process is based on new loop-oriented metrics that provide insight in key design issues. They help to determine which aspects of the design between data accesses and arithmetic logic unit (ALU)/control operations limit or allow leveraging loop acceleration opportunities. We profile some benchmarks from the signal and image processing fields, such as the Turbo Decoder and the JPEG algorithms, to illustrate how loop-oriented metrics help to point out aspects that limit or improve loop acceleration. The loop acceleration process was also used to explore design architectures that can leverage, as much as possible, the loop acceleration opportunities of the sum of absolute differences (SAD) algorithm.