Profiling tools for hardware/software partitioning of embedded applications

Authors:
Dinesh C. Suresh;Walid A. Najjar;Frank Vahid;Jason R. Villarreal;Greg Stitt
Affiliations:
University of California, Riverside, CA;University of California, Riverside, CA;University of California, Riverside, CA;University of California, Riverside, CA;University of California, Riverside, CA
Venue:
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Year:
2003

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Abstract

Loops constitute the most executed segments of programs and therefore are the best candidates for hardware software partitioning. We present a set of profiling tools that are specifically dedicated to loop profiling and do support combined function and loop profiling. One tool relies on an instruction set simulator and can therefore be augmented with architecture and micro-architecture features simulation while the other is based on compile-time instrumentation of gcc and therefore has very little slow down compared to the original program We use the results of the profiling to identify the compute core in each benchmark and study the effect of compile-time optimization on the distribution of cores in a program. We also study the potential speedup that can be achieved using a configurable system on a chip, consisting of a CPU embedded on an FPGA, as an example application of these tools in hardware/software partitioning.