Lex & yacc
A C compiler for a processor with a reconfigurable functional unit
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System
Journal of VLSI Signal Processing Systems
Instruction generation for hybrid reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The Garp Architecture and C Compiler
Computer
Profiling tools for hardware/software partitioning of embedded applications
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Energy Management for Dynamically Reconfigurable Heterogeneous Mobile Systems
IPDPS '01 Proceedings of the 10th Heterogeneous Computing Workshop â"" HCW 2001 (Workshop 1) - Volume 2
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In this paper, we describe a prototype software framework that implements a formalized methodology for partitioning computational intensive applications between reconfigurable hardware blocks of different granularity. A hybrid granularity reconfigurable generic architecture is considered for this methodology, so as the methodology is applicable to a large variety of hybrid reconfigurable architectures. Although, the proposed framework is parametrical in respect to the mapping procedures to the fine- and coarse-grain reconfigurable units, we provide mapping algorithms for these types of hardware. The experimental results show the effectiveness of the functionality partitioning framework. We have validated the framework using two real-world applications, an OFDM transmitter and a JPEG encoder. For the OFDM transmitter, a maximum clock cycles decrease of 82% relative to an all fine-grain mapping solution is achieved. The performance improvement for the JPEG is 44%.