Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System

Authors:
Marlene Wan;Hui Zhang;Varghese George;Martin Benes;Arthur Abnous;Vandana Prabhu;Jan Rabaey
Affiliations:
Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA;Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA;Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA;Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA;Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA;Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA;Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA
Venue:
Journal of VLSI Signal Processing Systems
Year:
2001

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Abstract

In this paper, we first present a reconfigurable architecture template for low-power digital signal processing, and then an energy conscious design methodology to bridge the algorithm to architecture gap. The energy efficiency of such an architecture and the effectiveness of the methodology are demonstrated in case study implementations targeting baseband voice processing and digital signal processing.