Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Network flow based circuit partitioning for time-multiplexed FPGAs
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Hardware-software co-design of embedded reconfigurable architectures
Proceedings of the 37th Annual Design Automation Conference
Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System
Journal of VLSI Signal Processing Systems
A super-scheduler for embedded reconfigurable systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Hardware-Software Codesign for Dynamically Reconfigurable Architectures
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Modifying Min-Cut for Hardware and Software Functional Partitioning
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
An evaluation of bipartitioning techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using reconfigurability to achieve real-time profiling for hardware/software codesign
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Design Space Exploration for Dynamically Reconfigurable Architectures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey
Journal of VLSI Signal Processing Systems
Run-time reconfigurable systems for digital signal processing applications: a survey
Journal of VLSI Signal Processing Systems
Genetic algorithms for hardware-software partitioning and optimal resource allocation
Journal of Systems Architecture: the EUROMICRO Journal
Thread warping: a framework for dynamic synthesis of thread accelerators
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Leveraging reconfigurability in the hardware/software codesign process
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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The main unique feature of dynamically reconfigurable systems is the ability to time-share the same reconfigurable hardware resources. However, the energy-delay cost associated with reconfiguration must be accounted for during hardware-software partitioning. We propose a method for mapping nodes of an application control flow graph either to software or reconfigurable hardware, explicitly targeting minimization of the energy-delay cost due to both computation and configuration. The addressed problems are energy-delay product minimization, delay-constrained energy minimization, and energy-constrained delay minimization. We show how these problems can be tackled by using network flow techniques, after transforming the original control flow graph into an equivalent network. If there are no constraints, as in the case of the energy-delay product minimization, we are able to generate an optimal solution in polynomial time.