MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Exact scheduling strategies based on bipartite graph matching
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Early evaluation techniques for low power binding
Proceedings of the 2002 international symposium on Low power electronics and design
Instruction generation and regularity extraction for reconfigurable processors
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Instruction generation for hybrid reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Predictability: definition, ananlysis and optimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Hardware-software bipartitioning for dynamically reconfigurable systems
Proceedings of the tenth international symposium on Hardware/software codesign
Effective graph theoretic techniques for the generalized low power binding problem
Proceedings of the 2003 international symposium on Low power electronics and design
An optimal algorithm for minimizing run-time reconfiguration delay
ACM Transactions on Embedded Computing Systems (TECS)
Achieving Design Closure Through Delay Relaxation Parameter
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A low power architecture for embedded perception
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Instruction scheduling using MAX-MIN ant system optimization
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Temperature-aware resource allocation and binding in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
Optimal reconfiguration sequence management
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Effective techniques for the generalized low-power binding problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Time-constrained scheduling of large pipelined datapaths
Journal of Systems Architecture: the EUROMICRO Journal
Managing the power resources of sensor networks with performance considerations
Computer Communications
An ILP based management protocol for wireless networks
ICCOM'05 Proceedings of the 9th WSEAS International Conference on Communications
Proceedings of the ICST 2nd international conference on Body area networks
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Emerging reconfigurable systems attain high peformance with embedded optimized cores. For mapping designs on such special architectures, synthesis tools, that are aware of the special capabilities of the underlying architecture are necessary. In this paper we are proposing an algorithm to perform simultaneous scheduling and binding, targeting embedded reconfigurable systems. Our algorithm differs from traditional scheduling methods in its capability of efficiently utilizing embedded blocks within the reconfigurable system. Our algorithm can be used to implement several other scheduling techniques, such as ASAP, ALAP, and list scheduling. Hence we refer to it as a super-scheduler. Our algorithm is a path-based scheduling algorithm. At each step, an individual path from the input DFG is scheduled. Our experiments with several DFG's extracted from MediaBench suit indicate promising results. Our scheduler presents capability to perform the trade-off between maximally utilizing the high-performance embedded blocks and exploiting parallelism in the schedule.