Competitive paging with locality of reference
Selected papers of the 23rd annual ACM symposium on Theory of computing
Strongly Competitive Algorithms for Paging with Locality of Reference
SIAM Journal on Computing
Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Scheduling designs into a time-multiplexed FPGA
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Network flow based circuit partitioning for time-multiplexed FPGAs
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Dynamically reconfigurable architecture for image processor applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On the complexity of loop fusion
Parallel Computing - Special issue on new trends on scheduling in parallel and distributed systems
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
A framework for reconfigurable computing: task scheduling and context management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Proceedings of the 39th annual Design Automation Conference
Computer Networks: The International Journal of Computer and Telecommunications Networking - Special issue on programmable networks
A super-scheduler for embedded reconfigurable systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
On computation and resource management in an FPGA-based computation environment
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Optimal integer delay budgeting on directed acyclic graphs
Proceedings of the 40th annual Design Automation Conference
Real-Time 2-D Feature Detection on a Reconfigurable Computer
CVPR '98 Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A dynamic reconfiguration run-time system
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Fast Partial Reconfiguration for FCCMs
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Configuration Caching Management Techniques for Reconfigurable Computing
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Configuration Compression for Virtex FPGAs
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Mapping data-parallel tasks onto partially reconfigurable hybrid processor architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A model-based extensible framework for efficient application design using FPGA
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The minimization of hardware size in reconfigurable embedded platforms
Proceedings of the 2008 ACM symposium on Applied computing
Customized kernel execution on reconfigurable hardware for embedded applications
Microprocessors & Microsystems
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Task Scheduling for Context Minimization in Dynamically Reconfigurable Platforms
Journal of Signal Processing Systems
Task scheduling for context minimization in dynamically reconfigurable platforms
EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
High-level synthesis with reconfigurable datapath components
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Efficient datapath merging for the overhead reduction of run-time reconfigurable systems
The Journal of Supercomputing
A modified merging approach for datapath configuration time reduction
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Energy-efficient scheduling on multi-FPGA reconfigurable systems
Microprocessors & Microsystems
An approach to manage reconfigurations and reduce area cost in hard real-time reconfigurable systems
ACM Transactions on Embedded Computing Systems (TECS)
Journal of Real-Time Image Processing
Meta-algorithms for scheduling a chain of coarse-grained tasks on an array of reconfigurable FPGAs
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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Reconfiguration delay is one of the major barriers in the way of dynamically adapting a system to its application requirements. The run-time reconfiguration delay is quite comparable to the application latency for many classes of applications and might even dominate the application run-time. In this paper, we present an efficient optimal algorithm for minimizing the run-time reconfiguration (context switching) delay of executing an application on a dynamically adaptable system. The system is composed of a number of cameras with embedded reconfigurable resources collaborating in order to track an object. The operations required to execute in order to track the object are revealed to the system at run-time and can change according to a number of parameters, such as the target shape and proximity. Similarly, we can assume that the applications comprising tasks are already scheduled and each of them has to be realized on the reconfigurable fabric in order to be executed.The modeling and the algorithm are both applicable to partially reconfigurable platforms as well as multi-FPGA systems. The algorithm can be directly applied to minimize the application run-time for the typical classes of applications, where the actual execution delay of the basic operations is negligible compared to the reconfiguration delay. We prove the optimality and the efficiency of our algorithm. We report the experimental results, which demonstrate a 2.5--40% improvement on the total run-time reconfiguration delay as compared to other heuristics.