Configuration prefetch for single context reconfigurable coprocessors
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Proceedings of the 6th international workshop on Hardware/software codesign
Reconfigurable computing: what, why, and implications for design automation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Algorithms for VLSI Design Automation
Algorithms for VLSI Design Automation
An optimal algorithm for minimizing run-time reconfiguration delay
ACM Transactions on Embedded Computing Systems (TECS)
Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling
ACM Transactions on Embedded Computing Systems (TECS)
Modeling and optimizing run-time reconfiguration using evolutionary computation
ACM Transactions on Embedded Computing Systems (TECS)
Lava and JBits: From HDL to Bitstream in Seconds
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Proceedings of the 42nd annual Design Automation Conference
Temporal floorplanning using the T-tree formulation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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To minimize the hardware fabrications in reconfigurable devices, this paper explores hardware synthesis to derive reconfiguration plans during the design time based on schedules derived by CAD tools, where a schedule includes the starting time, the execution time, and the intertask data transmissions for each task. We propose scheduling algorithms to derive optimal solutions for hardware descriptions with the same reconfiguration latency based on backward configuration and backward ordering strategies. For general cases, where a hardware description might be shared by tasks, we develop an algorithm based on a duplication merging strategy with performance evaluations. Our proposed algorithms could be applied after the hardware/software co-design procedures of task partitioning and scheduling to optimize the hardware requirements during the design time.