Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Partially Reconfigurable Cores for Xilinx Virtex
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A design flow for partially reconfigurable hardware
ACM Transactions on Embedded Computing Systems (TECS)
Exploiting Program Branch Probabilities in Hardware Compilation
IEEE Transactions on Computers
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
The minimization of hardware size in reconfigurable embedded platforms
Proceedings of the 2008 ACM symposium on Applied computing
Design, Debug, Deploy: The Creation of Configurable Computing Applications
Journal of Signal Processing Systems
Type-safe observable sharing in Haskell
Proceedings of the 2nd ACM SIGPLAN symposium on Haskell
IFL'09 Proceedings of the 21st international conference on Implementation and application of functional languages
Design, implementation, and verification of an adaptable processor in lava HDL
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Handshaking in kansas lava using patch logic
PADL'12 Proceedings of the 14th international conference on Practical Aspects of Declarative Languages
Processor design using a functional hardware description language
Microprocessors & Microsystems
Synchronous digital circuits as functional programs
ACM Computing Surveys (CSUR)
Hi-index | 0.01 |
The paper reports a design methodology that allows FPGA programming bitstreams to be generated in seconds starting from a very high level circuit description. High speed bitstream generation and manipulation is particularly important for reconfigurable computing systems that can not wait for the typical run times incurred by conventional flows. The preliminary version of this system can generate bitstreams from HDL source 12 times faster than the conventional flow and future work may offer significantly larger speed improvements.