PRISC: programmable reduced instruction set computers
PRISC: programmable reduced instruction set computers
Lava: hardware design in Haskell
ICFP '98 Proceedings of the third ACM SIGPLAN international conference on Functional programming
Observable Sharing for Functional Circuit Description
ASIAN '99 Proceedings of the 5th Asian Computing Science Conference on Advances in Computing Science
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Lava and JBits: From HDL to Bitstream in Seconds
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A reflective functional language for hardware design and theorem proving
Journal of Functional Programming
The Molen compiler for reconfigurable processors
ACM Transactions on Embedded Computing Systems (TECS)
Processor design using a functional hardware description language
Microprocessors & Microsystems
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This paper documents the development, implementation, and verification of a RISC microprocessor using the functional hardware description language Lava. Basic methods to describe hardware in Lava are introduced and extended towards implementation of instruction set and pipeline structure. Synthesis results for Cyclone II FPGA are presented and compared against a traditional VHDL-based design flow. A loosely coupled coprocessor interface used to accelerate application-specific code is introduced. To authors' best knowledge it is the first attempt to describe a complete von Neumann machine in Lava. Project experiences as well as directions for further improvement of Lava are summarized.