Partial Run-Time Reconfiguration Using JRTR
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
The swappable logic unit: a paradigm for virtual hardware
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Compilation tools for run-time reconfigurable designs
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Fast Partial Reconfiguration for FCCMs
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Automated Extraction of Run-Time Parameterizable Cores from Programmable Device Configurations
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Lava and JBits: From HDL to Bitstream in Seconds
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
| Hi-index | 0.00 |
A technique for rapidly generating configuration datastreams from high-level HDL-like constructs is introduced. This new technique allows a wide variety of client applications to send a fully placed netlist to a sever which routes the netlist and then generates a configuration datastream (either full or partial). The configuration datastream can then be used by the client to reconfigure hardware. This new technology provides an experimental infrastructure that can realize many existing abstractions for reconfigurable computing. This paper considers an implementation of configuration data graphs.