Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead
Journal of VLSI Signal Processing Systems
A Hybrid Prototyping Platform for Dynamically Reconfigurable Designs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
A Virtual Hardware Handler for RTR Systems
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
An optimal algorithm for minimizing run-time reconfiguration delay
ACM Transactions on Embedded Computing Systems (TECS)
Modeling and optimizing run-time reconfiguration using evolutionary computation
ACM Transactions on Embedded Computing Systems (TECS)
Optimal reconfiguration sequence management
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Achieving energy efficiency through runtime partial reconfiguration on reconfigurable systems
ACM Transactions on Embedded Computing Systems (TECS)
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One of the latest missions in custom computing is to exploit partial reconfiguration to accelerate the achievable performance for FPGAs for Custom Computing Machines. In this paper, we present a methodology for applying partial reconfiguration for general purpose programming. Fast runtime reconfiguration is achieved through the concepts of Configuration Data Graphs and Reconfiguration State Graphs. A simple implementation of this system using the VCC HOTworks board is also presented.