Dynamic reconfiguration of FPGAs
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
The Java environment for reconfigurable computing
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A dynamic reconfiguration run-time system
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Compilation tools for run-time reconfigurable designs
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Incremental reconfiguration for pipelined applications
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A Run-Time Reconfigurable ATM Switch
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
JBitsTM Implementations of the Advanced Encryption Standard (Rijndael)
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Using PARBIT to Implement Partial Run-Time Reconfigurable Systems
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
| Hi-index | 0.00 |
Much has been written about the design and performance advantages of partial Run-Time Reconfiguration (RTR) over the last decade. While the results have been promising, commercial support for partial RTR has lagged. Until the introduction of the Xilinx Virtex(tm) family of devices, no mainstream, commercial FPGA has provided support for this capability. In this paper we describe JRTR, a software package which provides direct support for partial run-time reconfiguration. Using a cache-based model, this implementation provides fast, simple support for partial run-time reconfiguration. While the current implementation is on the Xilinx Virtex family of devices using the JBits tool suite, this approach may be applied to any SRAM-based FPGA that provides basic support for RTR.