An FPGA-based hardware accelerator for image processing
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
Partial Run-Time Reconfiguration Using JRTR
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Implementation Approaches for Reconfigurable Logic Applications
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
A survey of active network research
IEEE Communications Magazine
A very large-scale switching system by using nested ring-based architecture
Computers and Electrical Engineering
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This paper shows how one single-chip ATM switch developed with ASIC technology has been modified to implement a reconfigurable ATM switch in a VIRTEX FPGA. With this new approach it is possible to develop a flexible ATM switch, using partial RTR to deploy new features to the network.