Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
A framework for reconfigurable computing: task scheduling and context management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Designing Run-Time Reconfigurable Systems with JHDL
Journal of VLSI Signal Processing Systems
Quantitative Analysis of FPGA-based Database Searching
Journal of VLSI Signal Processing Systems
Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead
Journal of VLSI Signal Processing Systems
Formally Analyzed Dynamic Synthesis of Hardware
The Journal of Supercomputing
A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Partial Run-Time Reconfiguration Using JRTR
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Combining Serialisation and Reconfiguration for FPGA Designs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Improved Functional Simulation of Dynamically Reconfigurable Logic
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Interface specification for reconfigurable components
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Debugging Techniques for Dynamically Reconfigurable Hardware
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Reconfigurable Computing for Augmented Reality
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Pipeline Vectorization for Reconfigurable Systems
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Customizing Graphics Applications: Techniques and Programming Interface
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Automated Extraction of Run-Time Parameterizable Cores from Programmable Device Configurations
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Modeling and optimizing run-time reconfiguration using evolutionary computation
ACM Transactions on Embedded Computing Systems (TECS)
Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey
Journal of VLSI Signal Processing Systems
Run-time reconfigurable systems for digital signal processing applications: a survey
Journal of VLSI Signal Processing Systems
Temporal floorplanning using the three-dimensional transitive closure subGraph
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A configuration system architecture supporting bit-stream compression for FPGAs
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Energy reduction by systematic run-time reconfigurable hardware deactivation
Transactions on High-Performance Embedded Architectures and Compilers IV
Simulation-based functional verification of dynamically reconfigurable systems
ACM Transactions on Embedded Computing Systems (TECS)
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This paper describes a framework and tools for automating the production of designs which can be partially reconfigured at run time. The tools include: a partial evaluator, which produces configuration files for a given design, where the number of configurations can be minimised by a process, known as compile-time sequencing; an incremental configuration calculator, which takes the output of the partial evaluator and generates an initial configuration file and incremental configuration files that partially update preceding configurations; and a tool which further optimises designs for FPGAs supporting simultaneous configuration of multiple cells. While many of our techniques are independent of the design language and device used, our tools currently target Xilinx 6200 devices. Simultaneous configuration, for example, can be used to reduce the time for reconfiguring an adder to a subtractor from time linear with respect to its size to constant time at best and logarithmic time at worst.