Codesign of graphics hardware accelerators
HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
View-independent environment maps
HWWS '98 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Procedural texture mapping on FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Compilation tools for run-time reconfigurable designs
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Pipeline Vectorization for Reconfigurable Systems
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Summed-area tables for texture mapping
SIGGRAPH '84 Proceedings of the 11th annual conference on Computer graphics and interactive techniques
Hardware supported bump mapping: a step towards higher quality real-time rendering
EGGH'95 Proceedings of the Tenth Eurographics conference on Graphics Hardware
Energy-efficient signal processing using FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
A Co-processor System with a Virtex FPGA for Evolutionary Computation
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
High Speed Homology Search Using Run-Time Reconfiguration
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Domain-Specific Modeling for Rapid Energy Estimation of Reconfigurable Architectures
The Journal of Supercomputing
Particle graphics on reconfigurable hardware
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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This paper identifies opportunities for customizing architectures for graphics applications, such as infrared simulation and geometric visualization. We have studied methods for exploiting custom data formats and datapath widths, and for optimizing graphics operations such as texture mapping and hidden-surface removal. Techniques for balancing the graphics pipeline and for run-time reconfiguration have been implemented. The customized architectures are captured in Handel-C, a C-like language supporting parallelism and flexible data size, and compiled for Xilinx 4000 and Virtex FPGAs. We have also developed an application-programming interface based on the OpenGL standard for automatic speedup of graphics applications, including the Quake 2 action game.