Improving functional density using run-time circuit reconfiguration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compilation tools for run-time reconfigurable designs
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Formal Verification of Reconfigurable Cores
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A design flow for partially reconfigurable hardware
ACM Transactions on Embedded Computing Systems (TECS)
Advanced Formal Verification
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Proceedings of the conference on Design, automation and test in Europe
ReChannel: Describing and simulating reconfigurable hardware in systemC
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Run-time integration of reconfigurable video processing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules
RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
VAPRES: a virtual architecture for partially reconfigurable embedded systems
Proceedings of the Conference on Design, Automation and Test in Europe
OSSS+R: a framework for application level modelling and synthesis of reconfigurable systems
Proceedings of the Conference on Design, Automation and Test in Europe
Short-Circuits on FPGAs Caused by Partial Runtime Reconfiguration
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Modeling Dynamically Reconfigurable Systems for Simulation-Based Functional Verification
FCCM '11 Proceedings of the 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines
Functionally verifying state saving and restoration in dynamically reconfigurable systems
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
RTL Simulation of High Performance Dynamic Reconfiguration: A Video Processing Case Study
IPDPSW '13 Proceedings of the 2013 IEEE 27th International Symposium on Parallel and Distributed Processing Workshops and PhD Forum
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Dynamically reconfigurable systems (DRS) implemented using field-programmable gate arrays (FPGAs) allow hardware logic to be partially reconfigured while the rest of the design continues to operate. By mapping multiple reconfigurable hardware modules to the same physical region of an FPGA, such systems are able to time-multiplex their modules at runtime and adapt themselves to changing execution requirements. This architectural flexibility introduces challenges for verifying system functionality. New simulation approaches are required to extend traditional simulation techniques to assist designers in testing and debugging the time-varying behavior of DRS. This article summarizes our previous work on ReSim, the first tool to allow cycle-accurate yet physically independent simulation of a DRS reconfiguring both its logic and state. Furthermore, ReSim-based simulation does not require changing the design for simulation purposes and thereby verifies the implementation-ready design instead of a variation of the design. We discuss the conflicting requirements of simulation accuracy and verification productivity in verifying DRS designs and describe our approach to resolve this challenge. Through a range of case studies, we demonstrate that ReSim assists designers in detecting fabric-independent bugs of DRS designs and helps to achieve verification closure of DRS design projects.