A scheduling and allocation method to reduce data transfer time by dynamic reconfiguration
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead
Journal of VLSI Signal Processing Systems
Implementation of Virtual Circuits by Means of the FIPSOC Devices
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Dynamic Constant Coefficient Convolvers Implemented in FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Constant Coefficient Multiplication Using Look-Up Tables
Journal of VLSI Signal Processing Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Incremental elaboration for run-time reconfigurable hardware designs
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Support for partial run-time reconfiguration of platform FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
A partitioning methodology that optimises the area on reconfigurable real-time embedded systems
EURASIP Journal on Applied Signal Processing
Self-Adaptive Networked Entities for Building Pervasive Computing Architectures
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
Parametric Design for Reconfigurable Software-Defined Radio
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Automatically mapping applications to a self-reconfiguring platform
Proceedings of the Conference on Design, Automation and Test in Europe
Run-time self-reconfigurable 2D convolver for adaptive image processing
Microelectronics Journal
System-level power-performance tradeoffs for reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Run-time generation of partial FPGA configurations
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Signal Processing Systems
Journal of Real-Time Image Processing
Simulation-based functional verification of dynamically reconfigurable systems
ACM Transactions on Embedded Computing Systems (TECS)
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The ability to provide flexibility and allow fine-grain circuit specialization make field programmable gate arrays (FPGA's) ideal candidates for computing elements within application-specific architectures. The benefits of gate-level specialization and reconfigurability can be extended by reconfiguring circuit resources at run-time. This technique, termed run-time reconfiguration (RTR), allows the exploitation of dynamic conditions or temporal locality within application-specific problems. For several applications, this technique has been shown to reduce the hardware resources required for computation. The use of this technique on conventional FPGA's, however, requires additional time for circuit reconfiguration. A functional density metric is introduced that balances the advantages of RTR against its associated reconfiguration costs. This metric is used to justify run-time reconfiguration against other more conventional approaches. Several run-time reconfigured applications are presented and analyzed using this approach.