Partial evaluation and automatic program generation
Partial evaluation and automatic program generation
Improving functional density using run-time circuit reconfiguration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SIGSOFT '98/FSE-6 Proceedings of the 6th ACM SIGSOFT international symposium on Foundations of software engineering
Incremental reconfiguration of multi-FPGA systems
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Pebble: A Language for Parametrised and Reconfigurable Hardware Design
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Run-Time Parameterizable Cores
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Automating Production of Run-Time Reconfigurable Designs
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Reconfigurable Shape-Adaptive Template Matching Architectures
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A High I/O Reconfigurable Crossbar Switch
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Incremental elaboration of scenario-based specifications and behavior models using implied scenarios
ACM Transactions on Software Engineering and Methodology (TOSEM)
A reconfigurable, power-efficient adaptive Viterbi decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Incremental compilation for parallel logic verification systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic data folding with parameterizable FPGA configurations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We present a new technique for compiling run-time reconfigurable hardware designs. Run-time reconfigurable embedded systems can deliver promising benefits over implementations in application specific integrated circuits (ASICs) or microprocessors. These systems can often provide substantially more computational power than microprocessors and support higher exibility than ASICs. The compilation of hardware during run time, however, can add significant run-time overhead to these systems. We introduce a novel compilation technique called incremental elaboration, which enables circuits to be dynamically generated during run time. We propose a set-based model for incremental elaboration, and explain how it can be used in the hardware compilation process. Our approach is illustrated by various designs, particulary those for pattern matching and shape-adaptive template matching.