Lower bounds for planar orthogonal drawings of graphs
Information Processing Letters
A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Improved methods for approximating node weighted Steiner trees and connected dominating sets
Information and Computation
A Highly Parallel FPL-Based Machine and Its Formal Verification
Selected papers from the Second International Workshop on Field-Programmable Logic and Applications, Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping
Incremental Compilation for Logic Emulation
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
Logic emulation with virtual wires
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hyperreconfigurable architectures and the partition into hypercontexts problem
Journal of Parallel and Distributed Computing
Incremental elaboration for run-time reconfigurable hardware designs
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Design Aspects of Multi-level Reconfigurable Architectures
Journal of Signal Processing Systems
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In reconfigurable computing, circuits implemented on multi-FPGA systems have to be incrementally modified. Since reconfiguring an FPGA is time-consuming, the time for reconfiguration depends on the number of FPGAs to be reconfigured. Our objective is to reduce the number of such FPGAs. In this paper, we consider the specific problem of incrementally reconfiguring a multi-FPGA system that utilizes the direct interconnection architecture, where routing connections between FPGAs are to neighbors that are near. This problem can be divided into a net addition problem and a net deletion problem. We show that the net addition problem is a generalization of the NP-complete Steiner tree problem. Our algorithm for this problem is based on an adaptation of the Klein-Ravi approximation algorithm for the node-weighted Steiner tree problem. As for the net deletion problem, we prove that it is NP-complete but the problem is solvable in polynomial time for tree topologies. Based on the algorithm for trees, we design an effective heuristic algorithm for the general net deletion problem. Finally, we present an algorithm for solving the incremental reconfiguration problem which handles both placement of new gates and inter-FPGA routing.