Configuration compression for FPGA-based embedded systems
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Incremental reconfiguration of multi-FPGA systems
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
On metrics for comparing routability estimation methods for FPGAs
Proceedings of the 39th annual Design Automation Conference
A Self-Reconfigurable Gate Array Architecture
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Efficient Self-Reconfigurable Implementations Using On-chip Memory
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
(Self-)reconfigurable Finite State Machines: Theory and Implementation
Proceedings of the conference on Design, automation and test in Europe
Configuration compression for the Xilinx XC6200 FPGA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design Aspects of Multi-level Reconfigurable Architectures
Journal of Signal Processing Systems
Multi-level reconfigurable architectures in the switch model
Journal of Systems Architecture: the EUROMICRO Journal
Multi-level reconfigurable architectures in the switch model
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
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Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit the changing needs of a computation during run time. The increasing flexibility of modern dynamically reconfigurable systems improves their adaptability to computational needs but also makes fast reconfiguration difficult because of the large amount of reconfiguration information which has to be transferred. However, even when a computation uses this flexibility it will not use it all the time. Therefore, we propose to make the potential for reconfiguration itself reconfigurable. Such architectures are called hyperreconfigurable. Different models of hyperreconfigurable architectures are proposed in this paper. We also study a fundamental problem that emerges on such architectures, namely, to determine for a given computation when and how the potential for reconfiguration should be changed during run time so that the reconfiguration overhead is minimal. It is shown that the general problem is NP-hard but fast polynomial time algorithms are given to solve this problem for special types of hyperreconfigurable architectures. We define two example hyperreconfigurable architectures and illustrate the introduced concepts for corresponding application problems.