Computational geometry: an introduction
Computational geometry: an introduction
On routability prediction for field-programmable gate arrays
DAC '93 Proceedings of the 30th international Design Automation Conference
RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Interconnect complexity-aware FPGA placement using Rent's rule
Proceedings of the 2001 international workshop on System-level interconnect prediction
Estimating routing congestion using probabilistic analysis
Proceedings of the 2001 international symposium on Physical design
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
On Routing Demand and Congestion Estimation for FPGAs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Accurate pseudo-constructive wirelength and congestion estimation
Proceedings of the 2003 international workshop on System-level interconnect prediction
A-priori wirelength and interconnect estimation based on circuit characteristics
Proceedings of the 2003 international workshop on System-level interconnect prediction
Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
Rapid and Reliable Routability Estimation for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
On metrics for comparing interconnect estimation methods for FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hyperreconfigurable architectures and the partition into hypercontexts problem
Journal of Parallel and Distributed Computing
On interactions between routing and detailed placement
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Compile-time area estimation for LUT-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Congestion estimation and localization in fpgas:: a visual tool for interconnect prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Interconnect management is a critical design issue for large FPGA based designs. One of the most important issues for planning interconnection is the ability to accurately and efficiently predict the routability of a given design on a given FPGA architecture. The recently proposed routability estimation procedure, fGREP [6], produced estimates within 3 to 4% of an actual detailed router. Other known routability estimation methods include RISA [5], Lois's [7] method and Rent's rule based methods [1] [11] [9]. Comparing these methods has been difficult because of the different reporting methods used by the authors. We propose a uniform reporting metric based on comparing the estimates produced with the results of an actual detailed router on both local and global levels. We compare all the above methods using our reporting metric on a large number of benchmark circuits and show that the enhanced fGREP method produces tight estimates that outperform most other techniques.