Congestion estimation and localization in fpgas:: a visual tool for interconnect prediction

Authors:
David Yeager;Darius Chiu;Guy Lemieux
Affiliations:
University of British Columbia, Vancouver, BC, Canada;University of British Columbia, Vancouver, BC, Canada;University of British Columbia, Vancouver, BC, Canada
Venue:
Proceedings of the 2007 international workshop on System level interconnect prediction
Year:
2007

Citing 14
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Abstract

In this paper, we are concerned with locating the most congested regions in FPGA designs before routing is completed. As well, we are interested in the amount of congestion in these locations relative to surrounding areas. If this estimation is done accurately and early enough, e.g. prior to routing or even prior to placement, the data can be used to avoid or spread out congestion before it becomes a problem. We implemented several estimation methods in the VPR tool set and visually compare estimation results to an actual routing congestion ma. We find that standard image processing techniques such as blending and peak saturation considerably improve the quality of estimation for all metrics.