Boolean satisfiability in electronic design automation
Proceedings of the 37th Annual Design Automation Conference
SAT with partial clauses and back-leaps
Proceedings of the 39th annual Design Automation Conference
Segmented channel routability via satisfiability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Congestion estimation and localization in fpgas:: a visual tool for interconnect prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
Scalable formula decomposition for propositional satisfiability
Proceedings of the Third C* Conference on Computer Science and Software Engineering
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In this paper we address the problem of detailed FPGA routing using Boolean formulation methods. In the context of FPGA routing where routing resources are fixed, Boolean formulation methods can prove the unroutability of a given circuit, which is a clear advantage over classical net-at-a-time approaches. Previous attempts at FPGA routing using Boolean methods were based on Binary Decision Diagrams (BDDs) which limited their scope to small FPGAs. In this paper we employ an efficient search-based Boolean satisfiability approach to solve the routing problem and show that such an approach extends the range of Boolean methods to larger FPGAs. Furthermore, we show the possibility that more relaxed formulations of the routing constraints, allowing higher degrees of freedom for net routing, can be easily accommodated. Preliminary experimental results suggest that our approach is quite viable for FPGAs of practical size.