On channel segmentation design for row-based FPGAs
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Effects of FPGA architecture on FPGA routing
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
FPGA routing and routability estimation via Boolean satisfiability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient routability check algorithms for segmented channel routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A comparative study of two Boolean formulations of FPGA detailed routing constraints
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Chaff: engineering an efficient SAT solver
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Solving difficult SAT instances in the presence of symmetry
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Efficient conflict driven learning in a boolean satisfiability solver
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Satisfiability-Based Detailed FPGA Routing
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Board-level multiterminal net assignment for the partial cross-bar architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Algorithms for an FPGA switch module routing problem with application to global routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Quantum logic synthesis by symbolic reachability analysis
Proceedings of the 41st annual Design Automation Conference
Exploiting hierarchy and structure to efficiently solve graph coloring as SAT
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Comparison of Boolean satisfiability encodings on FPGA detailed routing problems
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Routability checking for three-dimensional architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Complete SAT solver based on set theory
ICICA'12 Proceedings of the Third international conference on Information Computing and Applications
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Segmented channel routing is fundamental to the routing of row-based FPGAs. In this paper, we study segmented channel routability via satisfiability. Our method encodes the horizontal and vertical constraints of the routing problem as Boolean conditions. The routability constraint is satisfiable if and only if the net connections in the segmented channel are routable. Empirical results show that the method is time-efficient and applicable to large problem instances.