FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Exact switchbox routing with search space reduction
ISPD '00 Proceedings of the 2000 international symposium on Physical design
A comparative study of two Boolean formulations of FPGA detailed routing constraints
Proceedings of the 2001 international symposium on Physical design
sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing
Proceedings of the 2002 international symposium on Physical design
Faster SAT and smaller BDDs via common function structure
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
FORCE: a fast and easy-to-implement variable-ordering heuristic
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A fast pseudo-boolean constraint solver
Proceedings of the 40th annual Design Automation Conference
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Routing on field-programmable switch matrices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Board-level multiterminal net assignment for the partial cross-bar architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Design diagnosis using Boolean satisfiability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Satisfiability and integer programming as complementary tools
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Segmented channel routability via satisfiability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Maximum circuit activity estimation using pseudo-boolean satisfiability
Proceedings of the conference on Design, automation and test in Europe
Ordered escape routing based on Boolean satisfiability
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Comparison of Boolean satisfiability encodings on FPGA detailed routing problems
Proceedings of the conference on Design, automation and test in Europe
Defect-aware logic mapping for nanowire-based programmable logic arrays via satisfiability
Proceedings of the Conference on Design, Automation and Test in Europe
A constraint satisfaction approach for programmable logic detailed placement
SAT'13 Proceedings of the 16th international conference on Theory and Applications of Satisfiability Testing
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Guaranteeing or even estimating the routability of a portion of a placed field programmable gate array (FPGA) remains difficult or impossible in most practical applications. In this paper, we develop a novel formulation of both routing and routability estimation that relies on a rendering of the routing constraints as a single large Boolean equation. Any satisfying assignment to this equation specifies a complete detailed routing. By representing the equation as a binary decision diagram (BDD), we represent all possible routes for all nets simultaneously. Routability estimation is transformed to Boolean satisfiability, which is trivial for BDD's. We use the technique in the context of a perfect routability estimator for a global router. Experimental results from a standard FPGA benchmark suite suggest the technique is feasible for realistic circuits, but refinements are needed for very large designs.