FPGA routing and routability estimation via Boolean satisfiability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Enhancing Davis Putnam with extended binary clause reasoning
Eighteenth national conference on Artificial intelligence
A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints
IEEE Transactions on Computers
Adaptive eager boolean encoding for arithmetic reasoning in verification
Adaptive eager boolean encoding for arithmetic reasoning in verification
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Propagation via lazy clause generation
Constraints
Test Pattern Generation using Boolean Proof Engines
Test Pattern Generation using Boolean Proof Engines
PERT as an aid to logic design
IBM Journal of Research and Development
Robust Boolean reasoning for equivalence checking and functional property verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Lynx: a programmatic SAT solver for the RNA-folding problem
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
A cardinality solver: more expressive constraints for free
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
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This paper presents a Boolean SAT constraint satisfaction formulation of the detailed placement problem for programmable logic. The detailed placement problem is usually considered a poor candidate for a SAT-based solution due to complex timing constraints and the large size of the problem space. To overcome these challenges, we encode domain-specific knowledge into the problem formulation and add new features to the SAT solver. First, a Boolean encoding of timing constraints is presented that utilizes concepts from static timing analysis. Second, future cost clauses are added to the formulation to guide the SAT solver in a manner similar to A* search. Third, a dynamic clause generation approach is described that keeps the working problem size small by adding clauses on demand as the SAT solver explores the problem space. This includes dynamic cardinality clauses and dynamic addition of literals to cardinality clauses.