MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Journal of Electronic Testing: Theory and Applications
Incremental solving techniques for SAT-based ATPG
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Techniques for SAT-based constrained test pattern generation
Microprocessors & Microsystems
SAT-based generation of compressed skewed-load tests for transition delay faults
Microprocessors & Microsystems
A constraint satisfaction approach for programmable logic detailed placement
SAT'13 Proceedings of the 16th international conference on Theory and Applications of Satisfiability Testing
The influence of implementation type on dependability parameters
Microprocessors & Microsystems
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits
Journal of Electronic Testing: Theory and Applications
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In Test Pattern Generation using Boolean Proof Engines, we give an introduction to ATPG. The basic concept and classical ATPG algorithms are reviewed. Then, the formulation as a SAT problem is considered. As the underlying engine, modern SAT solvers and their use on circuit related problems are comprehensively discussed. Advanced techniques for SAT-based ATPG are introduced and evaluated in the context of an industrial environment. The chapters of the book cover efficient instance generation, encoding of multiple-valued logic, usage of various fault models, and detailed experiments on multi-million gate designs. The book describes the state of the art in the field, highlights research aspects, and shows directions for future work.