GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
New Techniques for Deterministic Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
Robust Search Algorithms for Test Pattern Generation
FTCS '97 Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS '97)
A Circuit SAT Solver With Signal Correlation Guided Learning
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ALAPTF: A NEW TRANSITION FAULTMODEL AND THE ATPG ALGORITHM
ITC '04 Proceedings of the International Test Conference on International Test Conference
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Test Pattern Generation using Boolean Proof Engines
Test Pattern Generation using Boolean Proof Engines
Combinational test generation using satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SPIRIT: a highly robust combinational test generation algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On Acceleration of SAT-Based ATPG for Industrial Designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Automatic test pattern generation (ATPG) based on the Boolean satisfiability (SAT) problem has recently been proven to be a beneficial complement to traditional methods. Efficient SAT techniques yield a robust fault classification. In this paper, we present methodologies to Improve the efficiency of SAT-based ATPG. First, we give a detailed run time analysis of a state-of-the-art SAT-based ATPG tool. By only taking Circuit partitions into account and applying incremental SAT solving, both SAT instance generation and SAT instance solving can be accelerated and the robustness of the ATPG process is increased. Besides the significant run time reduction of SAT-based ATPG, the methodology can additionally be used to improve the test set quality. The proposed techniques are applied for the stuck-at and for the transition fault model. A set of large industrial designs is used to show the efficiency of the approach.