New Techniques for Deterministic Test Pattern Generation

Authors:
Ilker Hamzaoglu;Janak H. Patel
Affiliations:
Center for Reliable & High-Performance Computing, University of Illinois, Urbana, IL 61801, USA;Center for Reliable & High-Performance Computing, University of Illinois, Urbana, IL 61801, USA
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
1999

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Abstract

This paper presents new techniques for speeding updeterministic test pattern generation for VLSI circuits. Thesetechniques improve the PODEM algorithm by reducing number ofbacktracks with a low computational cost. This is achieved by findingmore necessary signal line assignments, by detecting conflictsearlier, and by avoiding unnecessary work during test generation. Wehave incorporated these techniques into an advanced ATPG system forcombinational circuits, called ATOM. The performance results for theISCAS85 and full scan version of the ISCAS89 benchmark circuitsdemonstrated the effectiveness of these techniques on the testgeneration performance. ATOM detected all the testable faults andproved all the redundant faults to be redundant with a small numberof backtracks in a short amount of time.