ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Functional vector generation for HDL models using linear programming and 3-satisfiability
DAC '98 Proceedings of the 35th annual Design Automation Conference
Combinational equivalence checking using satisfiability and recursive learning
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Algorithms for solving Boolean satisfiability in combinational circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Enhancing simulation with BDDs and ATPG
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Boolean satisfiability in electronic design automation
Proceedings of the 37th Annual Design Automation Conference
SAT based ATPG using fast justification and propagation in the implication graph
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
A framework for low complexitgy static learning
Proceedings of the 38th annual Design Automation Conference
Accelerating boolean satisfiability through application specific processing
Proceedings of the 14th international symposium on Systems synthesis
An exact solution to the minimum size test pattern problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Bounded Model Checking Using Satisfiability Solving
Formal Methods in System Design
SAT with partial clauses and back-leaps
Proceedings of the 39th annual Design Automation Conference
SAT and ATPG: algorithms for Boolean decision problems
Logic Synthesis and Verification
SIVA: A System for Coverage-Directed State Space Search
Journal of Electronic Testing: Theory and Applications
An Overview of Backtrack Search Satisfiability Algorithms
Annals of Mathematics and Artificial Intelligence
A SAT Solver Using Reconfigurable Hardware and Virtual Logic
Journal of Automated Reasoning
Efficient conflict driven learning in a boolean satisfiability solver
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Faster SAT and smaller BDDs via common function structure
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
New Techniques for Deterministic Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
Why is Combinational ATPG Efficiently Solvable for Practical VLSI Circuits?
Journal of Electronic Testing: Theory and Applications
Computational Forensic Techniques for Intellectual Property Protection
IHW '01 Proceedings of the 4th International Workshop on Information Hiding
The Quest for Efficient Boolean Satisfiability Solvers
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
An algorithmic approach to optimizing fault coverage for BIST logic synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Conflict driven techniques for improving deterministic test pattern generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
SAT and ATPG: Boolean engines for formal hardware verification
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
20.2 New Techniques for Deterministic Test Pattern Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
CAMA: A Multi-Valued Satisfiability Solver
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Local Search for Boolean Relations on the Basis of Unit Propagation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
PFGASAT" A Genetic SAT Solver Combining Partitioning and Fuzzy Strategies
COMPSAC '04 Proceedings of the 28th Annual International Computer Software and Applications Conference - Volume 01
A software/reconfigurable hardware SAT solver
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient SAT solving: beyond supercubes
Proceedings of the 42nd annual Design Automation Conference
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Enhancing SAT-based equivalence checking with static logic implications
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Integration of supercubing and learning in a SAT solver
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Efficient Symmetry Breaking for Boolean Satisfiability
IEEE Transactions on Computers
B-Cubing: New Possibilities for Efficient SAT-Solving
IEEE Transactions on Computers
BerkMin: A fast and robust Sat-solver
Discrete Applied Mathematics
SAT-based ATPG using multilevel compatible don't-cares
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Ordered escape routing based on Boolean satisfiability
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Novel probabilistic combinational equivalence checking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A test generation framework for quantum cellular automata circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SymChaff: a structure-aware satisfiability solver
AAAI'05 Proceedings of the 20th national conference on Artificial intelligence - Volume 1
SATzilla: portfolio-based algorithm selection for SAT
Journal of Artificial Intelligence Research
Computing bounds for fault tolerance using formal techniques
Proceedings of the 46th Annual Design Automation Conference
Efficient symmetry breaking for boolean satisfiability
IJCAI'03 Proceedings of the 18th international joint conference on Artificial intelligence
An outlook on design technologies for future integrated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FRACTAL: efficient fault isolation using active testing
IJCAI'09 Proceedings of the 21st international jont conference on Artifical intelligence
Scalable formula decomposition for propositional satisfiability
Proceedings of the Third C* Conference on Computer Science and Software Engineering
Incremental solving techniques for SAT-based ATPG
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Solving satisfiability in combinational circuits with backtrack search and recursive learning
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
A model-based active testing approach to sequential diagnosis
Journal of Artificial Intelligence Research
Zchaff2004: an efficient SAT solver
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Automatic test pattern generation
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Building efficient decision procedures on top of SAT solvers
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Application of logic synthesis to the understanding and cure of genetic diseases
Proceedings of the 49th Annual Design Automation Conference
Evaluating component solver contributions to portfolio-based algorithm selectors
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
Techniques for SAT-based constrained test pattern generation
Microprocessors & Microsystems
SAT-based generation of compressed skewed-load tests for transition delay faults
Microprocessors & Microsystems
Accurate QBF-based test pattern generation in presence of unknown values
Proceedings of the Conference on Design, Automation and Test in Europe
Improved SAT-based ATPG: more constraints, better compaction
Proceedings of the International Conference on Computer-Aided Design
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We present a robust, efficient algorithm for combinational test generation using a reduction to satisfiability (SAT). The algorithm, Test Generation Using Satisfiability (TEGUS), solves a simplified test set characteristic equation using straightforward but powerful greedy heuristics, ordering the variables using depth-first search and selecting a variable from the next unsatisfied clause at each branching point. For difficult faults, the computation of global implications is iterated, which finds more implications than previous approaches and subsumes structural heuristics such as unique sensitization. Without random tests or fault simulation, TEGUS completes on every fault in the ISCAS networks, demonstrating its robustness, and is ten times faster for those networks which have been completed by previous algorithms. Our implementation of TEGUS can be used as a base line for comparing test generation algorithms; we present comparisons with 45 recently published algorithms. TEGUS combines the advantages of the elegant organization of SAT-based algorithms with the efficiency of structural algorithms