HANNIBAL: an efficient tool for logic verification based on recursive learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
SAT based ATPG using fast justification and propagation in the implication graph
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A machine program for theorem-proving
Communications of the ACM
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Efficient conflict driven learning in a boolean satisfiability solver
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
The Impact of Branching Heuristics in Propositional Satisfiability Algorithms
EPIA '99 Proceedings of the 9th Portuguese Conference on Artificial Intelligence: Progress in Artificial Intelligence
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
The complexity of theorem-proving procedures
STOC '71 Proceedings of the third annual ACM symposium on Theory of computing
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Testing of Digital Systems
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Design diagnosis using Boolean satisfiability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Advanced Formal Verification
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Post-verification debugging of hierarchical designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Efficiency of Multi-Valued Encoding in SAT-based ATPG
ISMVL '06 Proceedings of the 36th International Symposium on Multiple-Valued Logic
On the relation between simulation-based and SAT-based diagnosis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
IEEE Transactions on Computers
Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets
IEEE Transactions on Computers
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Redundancy and Don't Cares in Logic Synthesis
IEEE Transactions on Computers
Easily Testable Iterative Systems
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
CirCUs: a hybrid satisfiability solver
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Combinational test generation using satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust Boolean reasoning for equivalence checking and functional property verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test Generation for Model-Based Diagnosis
Proceedings of the 2008 conference on ECAI 2008: 18th European Conference on Artificial Intelligence
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The postproduction test of integrated circuits is crucial to ensure a high quality of the final product. This test is carried out by checking the correct response of the chip under predefined input stimuli – or test patterns. These patterns are calculated by algorithms for Automatic Test Pattern Generation (ATPG). The basic concepts and algorithms for ATPG are reviewed in this chapter. Then, an advanced SAT-based ATPG tool is introduced and emprically evaluated.