Automatic test pattern generation
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
SAT-based generation of compressed skewed-load tests for transition delay faults
Microprocessors & Microsystems
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This paper presents an asynchronous encoding scheme using a MVL(Multi-Value Logic). This scheme reduces not only the number of wires but also the switching activities. It is achieved by the two proposed data encoding methods, RT/NRT(Return to Ternary/ ...