Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Solving covering problems using LPR-based lower bounds
DAC '97 Proceedings of the 34th annual Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Mixed-Mode BIST Using Embedded Processors
Proceedings of the IEEE International Test Conference on Test and Design Validity
Scan-Encoded Test Pattern Generation for BIST
Proceedings of the IEEE International Test Conference
Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
IEEE Transactions on Computers
Multiple distributions for biased random test patterns
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Combinational test generation using satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LFSR-Based Deterministic TPG for Two-Pattern Testing
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
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Most approaches to the synthesis of built-in self test (BIST)circuitry use a manual choose-and-evaluate approach, where aparticular BISTgenerator is chosenandthen evaluatedby fault-simulatingthe design with the vectors that the chosen generatorgenerates. We develop an algorithmic synthesis-during-test approachin this paper, wherein the tasks of synthesizing the BISTlogic and directed test pattern generation (DTPG) are intertwinedto maximize the resulting fault coverage.Our approach is applicable to a variety of BIST strategiesincluding those that use linear- and nonlinear-feedback shiftregisters. We show how our method can be used to synthesizeLFSR polynomials, LFSR seeds, LFSR weights, nonlinearfeedback, or bit-fixing logic. Experimental data is presented.