Scan-Encoded Test Pattern Generation for BIST

Proptest: a property based test pattern generator for sequential circuits using test compaction

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Built-in test sequence generation for synchronous sequential circuits based on loading and expansion of test subsequences

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times

IEEE Transactions on Computers

An algorithmic approach to optimizing fault coverage for BIST logic synthesis

ITC '98 Proceedings of the 1998 IEEE International Test Conference

A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Test vector chains for increased targeted and untargeted fault coverage

Proceedings of the 2008 Asia and South Pacific Design Automation Conference

Improving linear test data compression

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

On test generation with test vector improvement

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Path selection for transition path delay faults

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Reducing the storage requirements of a test sequence by using a background vector

Proceedings of the Conference on Design, Automation and Test in Europe