The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
New methods of improving parallel fault simulation in synchronous sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Built-in test generation for synchronous sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An Efficient Algorithm for Sequential Circuit Test Generation
IEEE Transactions on Computers
Scan-Encoded Test Pattern Generation for BIST
Proceedings of the IEEE International Test Conference
On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits
ATS '98 Proceedings of the 7th Asian Test Symposium
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Random pattern testing for sequential circuits revisited
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
ACTIV-LOCSTEP: A Test Generation Procedure Based on Logic Simulation and Fault Activation
FTCS '97 Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS '97)
Simulator-oriented fault test generator
DAC '77 Proceedings of the 14th Design Automation Conference
Vector restoration based static compaction of test sequences for synchronous sequential circuits
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
LOCSTEP: A Logic Simulation-Based Test Generation Procedure
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
The Weighted Random Test-Pattern Generator
IEEE Transactions on Computers
An automatic test pattern generator for large sequential circuits based on genetic algorithms
ITC'94 Proceedings of the 1994 international conference on Test
Proptest: a property based test pattern generator for sequential circuits using test compaction
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Efficient spectral techniques for sequential ATPG
Proceedings of the conference on Design, automation and test in Europe
State and Fault Information for Compaction-Based Test Generation
Journal of Electronic Testing: Theory and Applications
Efficient Sequential Test Generation Based on Logic Simulation
IEEE Design & Test
Application of Tools Developed at the University of Iowa to ITC-99 Benchmarks
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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We describe a fault simulation based test generation procedure for synchronous sequential circuits. Several techniques are used to generate test sequences to achieve high fault coverages at low computational complexity. Experimental results presented demonstrate that the proposed procedure achieves fault coverages which are in all cases the same or higher than those achieved by existing procedures. The run times of the procedure are considerably smaller compared to the existing procedures.