A structure and technique for pseudorandom-based testing of sequential circuits
Journal of Electronic Testing: Theory and Applications
Genetic algorithms for VLSI design, layout & test automation
Genetic algorithms for VLSI design, layout & test automation
Proptest: a property based test pattern generator for sequential circuits using test compaction
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Efficient spectral techniques for sequential ATPG
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Fixed-Biased Pseudorandom Built-In Self-Test for Random-Pattern-Resistant Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Compaction-based test generation using state and fault information
ATS '00 Proceedings of the 9th Asian Test Symposium
A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Vector restoration based static compaction of test sequences for synchronous sequential circuits
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
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We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vector compaction. Two types of techniques are considered. One is based on the new states a sequential circuit is driven into, and the other is based on the new faults that are detected between consecutive iterations of vector compaction. These data modify an otherwise random selection of vectors, to bias vector sequences that cause the circuit to reach new states, and cause previously undetected faults to be detected. The biased vectors, when used to extend the compacted test set, provide a more intelligent selection of vectors. The extended test set is then compacted. Repeated applications of state and fault analysis, vector generation and compaction produce significantly high fault coverage using relatively small computing resources. We obtained improvements in terms of higher fault coverage, fewer vectors for the same coverage, or smaller number of iterations and time required, consistently for several benchmark circuits.