Freeze!: a new approach for testing sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A structure and technique for pseudorandom-based testing of sequential circuits
Journal of Electronic Testing: Theory and Applications
Time-efficient automatic test pattern generation systems
Time-efficient automatic test pattern generation systems
Designing Circuits with Partial Scan
IEEE Design & Test
An Efficient Algorithm for Sequential Circuit Test Generation
IEEE Transactions on Computers
Parial Scan Using Reverse Direction Empirical Testability
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Built-in test generation for synchronous sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A Novel Approach to Random Pattern Testing of Sequential Circuits
IEEE Transactions on Computers
Proptest: a property based test pattern generator for sequential circuits using test compaction
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Built-in generation of weighted test sequences for synchronous sequential circuits
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits
IEEE Transactions on Computers
Simulation based test generation for scan designs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
ETW '00 Proceedings of the IEEE European Test Workshop
Degree-Of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
19.1 Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Application of Tools Developed at the University of Iowa to ITC-99 Benchmarks
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Journal of Electronic Testing: Theory and Applications
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Random pattern testing methods are known to result in poor fault coverage for most sequential circuits unless costly circuit modification methods are employed. We propose a novel approach to improve the random pattern testability of sequential-circuits. We introduce the concept of holding signals at primary inputs and scan flip-flops for a certain length of time instead of applying a new random vector at each clock cycle. When a random vector is held at the primary inputs of the circuit under test or at the scan flip-flops, the system clock is applied and the primary outputs of the circuit are observed. The number of clock cycles, k, for which each random input is held at a fixed value before applying the next random vector, is determined by using testability analysis or a test pattern generator for a very small number of lines or faults in the circuit. The lines of faults that are analyzed are the primary inputs to flip-flops. The information obtained from the testability analysis or test generator is used to determine the number k of clock cycles for which each random vector is to be held constant without changing the signal values. The algorithm consists of simulating a sequential circuit systematically, possibly with partial scan, in conjunction with the hold method. The method is low cost and the results of our experiment on the benchmark circuits show that it is very effective in providing fault coverage close to the maximum obtainable fault coverage using random patterns with full scan.