Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
IEEE Transactions on Computers
STARBIST: scan autocorrelated random pattern generation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Built-in test generation for synchronous sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Proptest: a property based test pattern generator for sequential circuits using test compaction
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
IDDQ and AC Scan: The War Against Unmodelled Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
Scan-Encoded Test Pattern Generation for BIST
Proceedings of the IEEE International Test Conference
A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Random pattern testing for sequential circuits revisited
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
19.1 Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Best Methods for At-Speed Testing?
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Vector restoration based static compaction of test sequences for synchronous sequential circuits
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
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We describe an on-chip test generation scheme for synchronous sequential circuits that allows at-speed testing of such circuits. The proposed scheme is based on loading of (short) input sequences into an on-chip memory and expansion of these sequences on-chip into test sequences. Complete coverage of modeled faults is achieved by basing the selection of the loaded sequences on a deterministic test sequence T_0 and ensuring that every fault detected by T_0 is detected by the expanded version of at least one loaded sequence. Specifically, each input sequence S is constructed based on a different fault f and is extracted from T_0 around a time unit where f is detected by T_0. Experimental results presented for benchmark circuits show that the length of the sequence that needs to be stored on-chip at any given time is, on the average, 11 percent of the length of T_0 and that the total length of all the loaded sequences is, on the average, 48 percent of the length of T_0. These results are obtained by extracting each sequence S around the first detection time of a target fault f. These results are further improved by considering several time units for every target fault f and selecting the shortest possible sequence based on f.