Best Methods for At-Speed Testing?

Authors:
Coordinator: Sreejit Chakravarty; Intel
Affiliations:
-;-
Venue:
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Year:
1998

Citing 0
Cited 6

Built-in test sequence generation for synchronous sequential circuits based on loading and expansion of test subsequences

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An approach to test compaction for scan circuits that enhances at-speed testing

Proceedings of the 38th annual Design Automation Conference
Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times

IEEE Transactions on Computers
A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set

IEEE Transactions on Computers
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

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Abstract

At-speed testing is needed to screen defects that are not screened by stuck-at tests or IDDQ tests. As clocking frequencies increase (200, 400, 600, 600 MHz), detecting defects that prevent fast clocking becomes more important. What are the best methods for screening these defects? This panel and attendees will attempt to answer this question.