Improving the test quality for scan-based BIST using a general test application scheme
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Random limited-scan to improve random pattern testing of scan circuits
Proceedings of the 38th annual Design Automation Conference
Improving the proportion of at-speed tests in scan BIST
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Simulation based test generation for scan designs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
IDDQ and AC Scan: The War Against Unmodelled Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
Analysis of pattern-dependent and timing-dependent failures in an experimental test chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time
ATS '98 Proceedings of the 7th Asian Test Symposium
19.1 Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Best Methods for At-Speed Testing?
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
We describe a built-in test pattern generation method for scan circuits.The method is based on partitioning and storage of test sets.Under this method,a precomputed test set is partitioned into several sets containing values of different primary inputs or state variables.The on-chip test set is obtained by implementing the Cartesian product of the various sets.The sets are reduced as much as possible before they are stored on-chip in order to reduce the storage requirements and the test application time.