CrossCheck: a cell based VLSI testability solution
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A satisfiability-based test generator for path delay faults in combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Microprocessor IDDQ Testing: A Case Study
IEEE Design & Test
An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Analysis and Detection of Timing Failures in an Experimental Test Chip
Proceedings of the IEEE International Test Conference on Test and Design Validity
Detecting Delay Flaws by Very-Low-Voltage Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Quantitative analysis of very-low-voltage testing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On n-detection test sequences for synchronous sequential circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
6.3 Experimental Results for IDDQ and VLV Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
An Experimental Chip to Evaluate Test Techniques Part 1: Description of Experiment
An Experimental Chip to Evaluate Test Techniques Part 1: Description of Experiment
Proceedings of the conference on Design, automation and test in Europe
On test data compression and n-detection test sets
Proceedings of the 40th annual Design Automation Conference
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
On the Evaluation of Arbitrary Defect Coverage of Test Sets
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Stuck-Fault Tests vs. Actual Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A BIST Approach for Very Deep Sub-Micron (VDSM) Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Multiple-Output Propagation Transition Fault Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Testing for Resistive Opens and Stuck Opens
ITC '01 Proceedings of the 2001 IEEE International Test Conference
On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
ELF-Murphy Data on Defects and Test Sets
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Measure of Quality for n-Detection Test Sets
IEEE Transactions on Computers
Worst-Case and Average-Case Analysis of n-Detection Test Sets
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
N-detection under transparent-scan
Proceedings of the 42nd annual Design Automation Conference
Generation of broadside transition fault test sets that detect four-way bridging faults
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Forming N-detection test sets without test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Partitioned n-detection test generation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Forward-looking reverse order fault simulation for n-detection test sets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On clustering of undetectable single stuck-at faults and test quality in full-scan circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Non-uniform coverage by n-detection test sets
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-pattern n-detection stuck-at test sets for delay defect coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents the results for very detailed studies ofpattern and timing-dependent failures from the 309 dies inthe retest of an experimental test chip. 22 out of the 50CUTs with pattern-dependent failures had test escapes ifthe test sets were reordered. Some timing-dependentfailures became timing-independent combinational (TIC)defects at very low voltage. Multiple-detect single stuckfault test sets have high transition fault coverage. Mostdies with TIC or non-TIC defects were close to grossfailures or next to the wafer periphery.