IDDQ testing as a component of a test suite: the need for several fault coverage metrics
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
A General Purpose IDDQ Measurement Circuit
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
The Cost of Quality: Reducing ASIC Defects with IDDQ At-Speed Testing and Increased Fault Coverage
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Test Features of the HP PA7100LC Processor
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Low-Power Mode and IEEE 1149.1 Compliance - A Low-Power Solution
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Diagnosis Method Using ΔIDDQ Probabilistic Signatures: Theory and Results
Journal of Electronic Testing: Theory and Applications
Analysis of pattern-dependent and timing-dependent failures in an experimental test chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Production-Oriented Measurement Method for Fast and Exhaustive Iddq Tests
EDTC '97 Proceedings of the 1997 European conference on Design and Test
SHOrt voltage elevation (SHOVE) test for weak CMOS ICs
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
6.3 Experimental Results for IDDQ and VLV Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Test Method Evaluation Experiments & Data
ITC '00 Proceedings of the 2000 IEEE International Test Conference
IDDQ Characterization in Submicron CMOS
ITC '97 Proceedings of the 1997 IEEE International Test Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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A case study of the use of IDDQ testing in the design and testing of the Hewlett-Packard PA7100LC PA-RISC microprocessor. This 900, 000 transistor custom design supports IDDQ test to ensure high quality without compromising 100 MHz+ performance. Design guidelines, measurement techniques and results are presented.