Diagnosis of leakage faults with IDDQ
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
Algorithms for IDDQ measurement based diagnosis of bridging faults
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
Identifying defects in deep-submicron CMOS ICs
IEEE Spectrum
Failure Diagnosis of Structured VLSI
IEEE Design & Test
Microprocessor IDDQ Testing: A Case Study
IEEE Design & Test
IDDQ Test and Diagnosis of CMOS Circuits
IEEE Design & Test
On the Current Behavior of Faulty and Fault-Free ICs and the Impact on Diagnosis
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Fault Location with Current Monitoring
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Current Signatures: Application
Proceedings of the IEEE International Test Conference
Bridging Defects Resistance Measurements in a CMOS Process
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A novel built-in current sensor for I/sub DDQ/ testing of deep submicron CMOS ICs
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Current signatures [VLSI circuit testing]
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On estimating bounds of the quiescent current for I/sub DDQ/ testin
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
CMOS Digital Integrated Circuits Analysis & Design
CMOS Digital Integrated Circuits Analysis & Design
On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults
IEEE Transactions on Computers
Diagnosis Method Using ΔIDDQ Probabilistic Signatures: Theory and Results
Journal of Electronic Testing: Theory and Applications
Dynamic Power Supply Current Testing of CMOS SRAMs
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Current Testing Procedure for Deep Submicron Devices
Journal of Electronic Testing: Theory and Applications
Studies of the SEMATECH IDDq test data
Journal of Systems Architecture: the EUROMICRO Journal - Defect and fault tolerance in VLSI Systems
IC Diagnosis Using Multiple Supply Pad IDDQs
IEEE Design & Test
Replacing IDDQ Testing: With Variance Reduction
Journal of Electronic Testing: Theory and Applications
Current Testing Procedure for Deep Submicron Devices
ETW '00 Proceedings of the IEEE European Test Workshop
On the Comparison of IDDQ and IDDQ Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Computer-Aided Fault to Defect Mapping (CAFDM) for Defect Diagnosis
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Empirical Study on the Effects of Test Type Ordering on
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Improving Delta-IDDQ-based test methods
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Histogram Based Procedure for Current Testing of Active Defects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Process-variation-aware Iddq diagnosis for nano-scale CMOS designs - the first step
Proceedings of the Conference on Design, Automation and Test in Europe
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The purpose of this paper is to present experimentalresults validating a diagnosis method based on differentialIddq probabilistic signatures and on maximum likelihoodestimation. First, SEMATECH Project S121 data is usedto support assumptions about current behavior. Thenresults obtained from an IC monitor containingcontrollable faults clearly show the capability of themethod to identify the type of actual activated faults, inspite of a strong experimental current standard variation.These results validate previous simulation procedures,which are applied to estimate what can be expected withmore common current standard variations.