On the generation of small dictionaries for fault location
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Algorithms for IDDQ measurement based diagnosis of bridging faults
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
On adaptive diagnostic test generation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A novel wavelet transform based transient current analysis for fault detection and localization
Proceedings of the 39th annual Design Automation Conference
IDDQ Test and Diagnosis of CMOS Circuits
IEEE Design & Test
Fault Detection and Location Using IDD Waveform Analysis
IEEE Design & Test
Current Signatures: Application
Proceedings of the IEEE International Test Conference
A Comparison of Defect Models for Fault Location with IDDQ Measurements
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results
ITC '98 Proceedings of the 1998 IEEE International Test Conference
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Eliminating the Ouija® Board: Automatic Thresholds and Probabilistic IDDQ Diagnosis
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Fault Simulation Model for i{DDT} Testing: An Investigation
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Extrapolation, Interpolation, and Smoothing of Stationary Time Series
Extrapolation, Interpolation, and Smoothing of Stationary Time Series
Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method
IEEE Design & Test
Calibrating power supply signal measurements for process and probe card variations
DBT '04 Proceedings of the 2004 IEEE International Workshop on Defect Based Testing
Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay
Journal of Electronic Testing: Theory and Applications
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This paper describes a new fault localization method that is based on the analysis of power supply transient signals. Impulse response functions derived from the power grid are used to de-construct the measured power port transient signals into a set of gate level transients generated by the logic gates as signals propagate along paths in the circuit. By comparing these gate transients with those obtained from a defect-free chip or simulation model, it is possible to identify anomalies produced by defects and to locate them to specific path segments in the layout. Impulse response functions are used to significantly reduce both the attenuation effects of the power grid on the gate-generated transients and the chip-to-chip impedance variations in the power grid and test environment. Non-linear calibration techniques are proposed to reduce the chip-to-chip variations in path delays introduced by process variations. The procedure is demonstrated using simulation experiments to locate the position of defects to one or a small group of gates.