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In today's technologies, resistive shorting and open defectsare becoming more predominant. Conventional fault models,and tools based on these models are becoming inadequatein addressing these defects resulting from new failuremechanisms. In prior works i{DDT} testing techniques havebeen shown to detect resistive defects. However, in order toincorporate i{DDT} based methods into production test flows,it is necessary to develop a fault simulation strategy toenable ATPG and fault coverage to be determined. To ourknowledge, no practical technique exists to perform faultsimulation for i{DDT} based methods. At the heart of the difficultyof developing a fault simulation strategy is the analognature of the test observable. In this paper we investigate afault simulation model that partitions the task of simulatingthe CUT (chip under test) into linear and non-linear components.We also propose a path isolation strategy for core-logicas a means of reducing the computational complexityinvolved in deriving i{DDT} signals in the non-linear portion.More specifically an Impulse Response based method isderived to eliminate the need for transient simulations ofthe entire CUT.